An Application of Add-based Timing Analysis to Combinational Low Power Re-synthesis

Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing, that is, slowing down gates without decreasing the speed of the logic network. Recently we have proposed a symbolic procedure which exploits the compactness of the ADD data structure to accurately calculate the arrival times at each node of a circuit for any primary input vector. In this paper we extend our timing analysis tool to the symbolic calculation of required times and slacks, and we use this information to identify gates of the circuit that can be re-sized. The nice feature of our approach is that it takes into account the presence of false paths naturally, that is, false paths in the network do not have to be handled by ad-hoc techniques. As shown by the experimental results, circuits re-synthesized with the technique we present in this paper are guaranteed to be at least as fast as the original implementations, but smaller and substantially less power-consuming. Our methods inproves power consumption on average by 28% and in one case by as much as 49%.